To improve device performance, a trend is developing for replacing conventional “bulk” silicon wafers with so-called silicon-on-insulator (“SOI”) wafers. The advantage of SOI technology is that the silicon in which transistors are made is not in electrical contact with the remainder of the wafer, such that no cross-talk among transistors takes place through the wafer bulk. The transistors are more effectively electrically isolated from one another.
SOI technology typically employs a thin (e.g., about 100 nm) insulating layer between the active semiconductor layer and the wafer, across the entire wafer or at least in those areas where active devices will be formed in the semiconductor layer. Silicon oxide, silicon nitride, or a combination of the two are typically employed as the insulating layer. These materials are amorphous, have excellent electrical properties, and the technology for integrating silicon nitride and/or silicon oxide is very well developed.
Two conventional technologies have been developed forming the SOI structures. One technology, known as SIMOX, starts with a semiconductor structure such as a silicon wafer and employs high energy implantation of oxygen atoms to form an oxide layer greater than about 100 nm below the surface of the silicon wafer. High temperature annealing then forms a buried silicon oxide, and at the same time repairs crystal defects in the surface silicon that are created by implantation. The surface silicon remains a semiconductor material, and the crystal structure thereof is restored by the annealing process. These steps are rather expensive, however, and the quality of the insulating layer and the active silicon thereover is somewhat compromised.
Another method for forming SOI structures is based on bonding a sacrificial silicon wafer onto an oxidized silicon wafer. By grinding or other thinning process, the sacrificial silicon wafer is reduced to a very thin, active semiconductor layer over the oxide from the other substrate. The thinning process, however, is critical to achieving high quality in the SOI structure, since the ultimately desired thickness uniformity of the active semiconductor layer is about 5 nm±0.1 nm. Furthermore, the bonding and thinning processes are complicated and rather expensive.
Strained silicon is utilized to increase carrier mobility and thus the operating speed of transistors. Typically a thin layer of silicon germanium (SiGe) is formed on a substrate and a very thin layer of silicon is deposited over the SiGe. Silicon has a smaller lattice constant than germanium, and when the silicon layer is grown on relaxed SiGe, the silicon atoms tend to align themselves with the more widely spaced atoms in the underlying layer. As a result, the top silicon layer is stretched, or strained, allowing electrical carriers to flow with less resistance.
Strained silicon and SOI are complementary technologies and several attempts have been made to fabricate SiGe-On-Insulator (SGOI) substrates.